1. Field of the Invention
The present invention relates to the field of time shared buses used by digital computers for information transfers.
2. Prior Art
Various types of bus structures for communication between the various elements of a computer system are well known in the prior art. Such structures include both unidirectional and bidirectional structures, and associated protocol, for both synchronous and asynchronous communication. While it would not be appropriate to provide a treatise herein on bus structures, it may be useful to generally describe a specific structure which has been particularly commercially successful and to note certain characteristics and limitations thereof.
In particular, the PDP-11, manufactured by Digital Equipment Corporation (DEC), utilizes a bus structure referred to by DEC as the Unibus, wherein a CPU, memory and peripheral devices are all coupled in parallel on a bidirectional bus. The bus itself is an asynchronous bus comprising a set of bidirectional address lines, a set of bidirectional data lines and a set of control lines. In general, communication between any two units on the bus is achieved in a master-slave relationship, with the unit initiating the communication serving as the master and the other unit serving as the slave. Usually the CPU will be one of the two units in any bus operation, in which case the CPU will take the position of the master, though inherent in the bus structure is a direct memory access capability not involving the CPU.
In a typical bus operation for the Unibus, both the address bus and the data bus are busy throughout most of the time required for the bus operation. By way of specific example, when the CPU addresses memory for an instruction or for an operand, the CPU seizes the bus and asserts the memory address and control signals thereon. The bus will remain tied up until the address is decoded, the data at the decoded location is placed on the bus and is received by the CPU. Consequently, even though separate address and data busses are provided, time sharing of the busses with other units is substantially impossible. Further, because the bus is tied up not only during the address and data communication times, but also throughout the memory (or other unit) cycle, bus operations may be relatively slow dependent upon the speed of the units on the bus. This is not to say that the bus does not have certain advantages, particularly with respect to its flexibility with respect to both hardware and software, though for the foregoing reasons, speed is not one of its greater assets.
Also in recent years there has been an increasing interest in multiprocessing wherein two or more central processing units are coupled to the same bus so that each processing unit will have access to all the other units on the bus, whereby the processing load may be shared or distributed between the processing units. It is clear that in such applications, many prior art bus structures such as the Unibus hereinbefore described are not appropriate for such multiprocessing applications, as a single processor normally ties up the bus most of the time, preventing any substantial gain by placing a second processor thereon. It is clear therefore, that a highly efficient bus structure is required if true multiprocessing with two or more processors on the same bus structure is to be achieved.
In addition to the foregoing, there has recently been increased emphasis on low cost and fault tolerant computer designs. In that regard, the number of bus lines required within a particular computer has a significant effect on the cost of the computer, as it grossly affects the cost and complexitiy of the backplane thereof and generally is reflected in an overall parts count for the computer. The number of lines has an even greater effect on the reliability of a computer, as connector contact failures are a common source of failure, and numerous contacts to each bus line are required in substantially all computer systems.